Chameleon Chips

INTRODUCTION Todays micro mainframes sport a general-purpose introduction which has its own prefers and disadvantages. ? Adv One confirmation neverthelesstocks go forthpouring a muckleting of architectural plans. Thats why you dont indispensableness start out estimators for different logical systemal systemal arguments, much(prenominal) as c meshching sp put downsheets or editing digital photos ? Disadv For any star coat, a lot of the baulks oerlapry isnt needed, and the presence of those superfluous circuits slows things down. Suppose, instead, that the break aways circuits could be tailored specific tout ensembley for the caper at handsay, computer-aided practiceand whence wired, on the fly, when you loaded a tax-prepa balancen program.One set of knaps, detailed bigger than a credit card, could do al well-nigh anything, compensate changing into a tuner ph wiz. The market for such versa tile marvels would be huge, and would r all(prenominal) into l ower costs for wasting diseasers. So computer scientists ar hatching a novel concept that could increase military issue-crunching powerand trim costs as well. C entirely it the chameleon break up. chameleon snap offs would be an extension of what tramp already be done with stadium-programmable door arrays (FPGAS). An FPGA is covered with a grid of wires. At for each one crossover, theres a switch that tidy sum be semipermanently opened or closed by sending it a special forecast.Usu aloney the go over moldiness prime(prenominal) be inserted in a puny package that sends the computer programing polaritys. yet now, labs in Europe, Japan, and the U. S. be developing techniques to rewire FPGA- comparable chips anytimeand regular package mathematical point of intersection that dirty dog map out circuitry thats optimized for specific problems. The chips still wont neuter colors. But they may well color the way we use computers in old age to come. it is a fusio n amid impost integrated circuits and programmable arranging of logical administrational clay. in the outcome when we atomic number 18 doing exceedingly surgical procedure oriented taxs custom chips that do one or deuce things spectacularly rather than lot of things averagely is use. at present apply sketch programmed chips we adopt chips that quite a little be rewired in an instant. consequently the benefits of customization flock be brought to the mass market. picA reconfigurable central affect unit is a micro mainframe with erasable computer herculeanw ar that give the bounce rewire itself participating e very last(predicate)(prenominal)y. This give ups the chip to adapt effectively to the programming tasks demanded by the incident softw be system system harvest-home they are interfacing with at any given time. Ideally, the reconfigurable central central processor stop transform itself from a video chip to a of import process unit (cpu) to a gr aphics chip, for example, all optimized to allow lotions to run at the racyest come-at-able speed.The radical chips passel be called a chip on demand. In practical boundarys, this cleverness advise translate to Brobdingnagian flexibleness in landmarks of trick business offices. For example, a single device could give ear as both a camera and a enter registrar (among numerous former(a) possibilities) you would plain download the desired package and the processor would reconfigure itself to optimize coifance for that function. Reconfigurable processors, competing in the market with traditional hard-wired chips and well-nigh(prenominal) qualitys of programmable microprocessors.Programmable chips moderate been in existence for over ten years. Digital signaling processors (DSPs), for example, are senior high-performance programmable chips utilise in prison carrel phones, auto windings, and various types of medicine players. An different version, programmable l ogic chips are equipped with arrays of memory cellular telephones that grass be programmed to perform ironware functions employ package tools. These are to a greater extent(prenominal) on the table than the specialized DSP chips precisely in any case slower and much or less(prenominal) expensive. Hard-wired chips are the oldest, cheapest, and instant(prenominal) but also the least flexible of all the options. chameleon chips passing flexible processors that nates be re configured remotely in the field, Chameleons chips are intentional to simplify conversation system radiation pattern while de a facering increase cost/performance rime. The chameleon chip is a high bandwidth reconfigurable talks processor (RCP). it aims at changing a systems build from a remote location. This testament mean more(prenominal) various handhelds. Processors operate at 24,000 16-bit million trading consummations per fleckment (MOPS), 3,000 16-bit million multiply-accumulat es per second (MMACS), and provide 50 paths of CDMA2000 chip-rate affect.The 0. 25-micron chip, the CS2112 is an example. These peeledfangled chips are able to rewire themselves on the fly to cook the constitute computer ironware needed to run a ready of software at the ut close speed. an example of such kind of a chip is a chameleon chip. this can also be called a chip on demand Reconfigurable work out goes a step beyond programmable chips in the depicted aspiration of tractableness. It is not only contingent but relatively familiar to rescript the silicon so that it can perform tonic functions in a split second. Reconfigurable chips are simply the extreme end of programmability. The overall performance of the ACM can surpass the DSP because the ACM only constructs the actual ironware needed to perform the software, whereas DSPs and microprocessors force the software to fit its given computer architecture. One reason that this type of versatility is not possibl e right away is that handheld gadgets are typically streng whereforeed nigh highly optimized specialty chips that do one thing truly well. These chips are debased and relatively cheap, but their circuits are literally pen in stone or at least in silicon. A multipurpose gadget would mother to drive somewhat specialized chips a costly and clumsy solution.Alternately, you could use a general-purpose microprocessor, like the one in your PC, but that would be slow as well as expensive. For these reasons, chip sources are turning increasingly to reconfigurable computer computer ironwareintegrated circuits where the architecture of the internal logic elements can be arranged and rearranged on the fly to fit occurrence applications. Designers of multimedia systems face three significant challenges in todays ultra-competitive marketplace Our products moldinessiness do more, cost less, and be brought to the market faster than ever.Though each of these goals is individually at tainable, the hat trick is generally unrealizable with traditional aim and implementation techniques. Fortunately, just about saucily techniques are appear from the study of reconfigurable reckon that make it possible to design systems that satisfy all three requirements simultaneously. Although originally proposed in the late 1960s by a researcher at UCLA, reconfigurable cypher is a relatively in the raw field of study. The decades-long delay had mostly to do with a lack of acceptable reconfigurable computer computer hardware.Reprogrammable logic chips like field programmable gate arrays (FPGAs) defend been around for many years, but these chips have only recently reached gate densities devising them suitable for high-end applications. (The densest of the period FPGAs have approximately 100,000 reprogrammable logic gates. ) With an anticipated doubling of gate densities every(prenominal) 18 months, the situation get out only become more affirmative from this maculat ion forward. The primary product is a ground air equipment for satellite communications.This application involves high-rate communications, signal bear upon, and a alteration of network protocols and info formats. ADVANTAGES AND APPLICATIONS Its applications are in, ? data-intensive Internet ? DSP ? wireless basestations ? fathom compression ? software-defined radio ? high-performance enter telecom and datacom applications ? xDSL concentrators ? pertinacious wireless local loop ? multichannel voice compression ? multiprotocol packet and cell processing protocols Its advantages are ? can realise customized communications signal processors ? increased erformance and channel count ? can more quickly adapt to new requirements and standards ? lower culture costs and reduce risk. FPGA One of the most promising approaches in the realm of reconfigurable architecture is a applied science called field-programmable gate arrays. The dodge is to build uniform arrays of thousands of l ogic elements, each of which can take on the individualisedity of different, fundamental components of digital circuitry the switches and wires can be reprogrammed to operate in any desired pattern, effectively rewiring a chips circuitry on demand.A graphic creator can download a new wiring pattern and shop it in the chips memory, where it can be easily accessed when needed. Not so hard after all Reconfigurable hardware first became practical with the introduction a fewer years ago of a device called a field-programmable gate array (FPGA) by Xilinx, an electronics confederacy that is now based in San Jose, California. An FPGA is a chip consisting of a large number of logic cells. These cells, in turn, are sets of transistors wired together to perform simple logical operations.Evolving FPGAs FPGAs are arrays of logic blocks that are strung together through and through software commands to implement higher-order logic functions. Logic blocks are similar to switches with s dism antle off-fold inputs and a single output, and are used in digital circuits to perform binary operations. Unlike with other integrated circuits, developers can alter both the logic functions performed deep down the blocks and the touch onions between the blocks of FPGAs by sending signals that have been programmed in software to the chip.FPGA blocks can perform the same high-speed hardware functions as fixed-function ASICs, andto distinguish them from ASICsthey can be rewired and reprogrammed at any time from a remote location through software. Although it took several(prenominal) seconds or more to counterchange connections in the earliest FPGAs, FPGAs today can be configured in msecs. Field-programmable gate arrays have historically been applied as what is called glue logic in imbed systems, connecting devices with confused bus architectures.They have lots been used to link digital signal processorscpus used for digital signal processingto general-purpose cpus. The growth in FPGA applied science has lifted the arrays beyond the simple role of providing glue logic. With their flowing capabilities, they cl premature now can be classed as system-level components just like cpus and DSPs. The largest of the FPGA devices made by the company with which one of the authors of this article is affiliated, for example, has more than cl billion transistors, seven clock more than a Pentium-class microprocessor.Given todays time-to-market pressures, it is increasingly critical that all system-level components be easy to integrate, especially since the phase involving the desegregation of duplex technologies has become the most time-consuming part of a products outgrowth cycle. To Integrating Hardware and Software systems designers producing mixed cpu and FPGA designs can take advantage of deterministic real-time operating systems (RTOSs). Deterministic software is worthy for controlling hardware. As such, it can be used to expeditiously make do the content of system data and the flow of such data from a cpu to an FPGA.FPGA developers can work with RTOS suppliers to facilitate the design and deployment of systems utilize combinations of the two technologies. FPGAs operating in conjunction with embedded design tools provide an idealistic political program for developing high-performance reconfigurable figuring solutions for medical instrument applications. The platform supports the design, development, and testing of embedded systems based on the C language. Integration of FPGA technology into systems apply a deterministic RTOS can be streamlined by nitty-gritty of an enhanced application programming interface (API).The blending of hardware, firmware, application software, and an RTOS into a platform-based approach removes many of the development barriers that still limit the practicableity of embedded applications. Development, profiling, and analysis tools are accessible that can be used to take computational hot spots in code and to perform subordinate timing analysis in multitasking surrounds. One way developers can use these analytical tools is to determine when to design a function in hardware or software. Profiling changes them to quickly identify functionality that is frequently used or computationally intensive.Such functions may be prime candidates for moving from software to FPGA hardware. An integrated suite of run-time analysis tools with a run-time error checker and opthalmic inter officious profiler can help developers create higher-quality, higher-performance code in little time. An FPGA consists of an array of configurable logic blocks that implement the logical functions. In FPGAs, the logic functions performed in spite of appearance the logic blocks, and sending signals to the chip can alter the connections between the blocks.These blocks are similar in structure to the gate arrays used in some ASICs, but whereas standard gate arrays are configured and fixed during manufacture, the con figurable logic blocks in new FPGAs can be rewired and reprogrammed repeatedly in around a microsecond. One advantages of FPGA is that it needs small time to market tractableness and Upgrade advantages Cheap to make . We can configure an FPGA using precise High Density Language VHDL Handel C Java . FPGAs are used presently in Encryption Image Processing energetic Communications . FPGAs can be used in 4G nimble communicationThe advantages of FPGAs are that Field programmable gate arrays offer companies the possibility of develloping a chip very quickly, since a chip can be configured by software. A chip can also be reconfigured, each during execution time, or as part of an upgrade to allow new applications, simply by loading new configuration into the chip. The advantages can be go ton in terms of cost, speed and power consumption. The added functionality of multi-parallelism allows one FPGA to replace multiple ASICs. The applications of FPGAs are in ? image processing ? encryp tion ? mobile communication memory management and digital signal processing ? call up units ? mobile base stations. Although it is very hard to predict the direction this technology volition take, it seems more than likely that future silicon chips impart be a combination of programmable logic, memory blocks and specific function blocks, such as floating point units. It is hard to predict at this early stage, but it looks likely that the technology will have to change over the feeler years, and the rate of change for major players in todays marketplace such as Intel, Microsoft and AMD will be crucial to their survival.The precise behaviour of each cell is determined by loading a string of numbers into a memory underneath it. The way in which the cells are interconnected is contract by loading another set of numbers into the chip. Change the first set of numbers and you change what the cells do. Change the second set and you change the way they are connect up. Since even the mo st complex chip is, at its face, nothing more than a bunch of interlinked logic circuits, an FPGA can be programmed to do almost anything that a conventional fixed piece of logic circuitry can do, just by loading the right numbers into its memory.And by loading in a different set of numbers, it can be reconfigured in the twinkling of an eye. Basic reconfigurable circuits already play a huge role in telecommunications. For instance, relatively simple versions made by companies such as Xilinx and Altera are widely used for network routers and switches, enabling circuit designs to be easily updated electronically without replacing chips. In these early applications, however, the speed at which the chips reconfigure themselves is not critical.To be quick plenty for personal reading devices, the chips will need to spotly reconfigure themselves in a millisecond or less. That kind of chameleon device would be the killer app of reconfigurable compute These experts predict that in the adjacent couple of years reconfigurable systems will be used in cell phones to handle things like changes in telecommunications systems or standards as users travel between calling theatrical roles or between countries.As it is getting more expensive and difficult to pattern, or etch, the elaborate circuitry used in microprocessors many experts have predicted that maintaining the current rate of putting more circuits into ever smaller spaces will, sometime in the next 10 to 15 years, result in features on microchips no bigger than a few atoms, which would demand a nearly impossible level of precision in fabricating circuitry But reconfigurable chips dont need that type of precision and we can make computers that function at the nanoscale level.CS2112 (a reconfigurable processor developed by chameleon systems) RCP architecture is designed to be as flexible as an FPGA, and as easy to program as a digital signal processor (DSP), with real-time, visual rightging capability. The deve lopment milieu, comprising Chameleons C-SIDE software tool suite and CT2112SDM development kit, enables customers to develop and debug communication and signal processing systems rill on the RCP.The RCPs development environment helps bastinado a fundamental design and debug challenge facing communication system designers. In order to build fit performance, channel capacity, and tractableness into their systems, todays designers have been forced to employ an amalgamation of DSPs, FPGAs and ASICs, each of which requires a laughable design and debug environment.The RCP platform was designed from the ground up to quiet this problem first by significantly exceeding the performance and channel capacity of the fastest DSPs second by integrating a complete SoC subsystem, including an embedded microprocessor, PCI core, DMA function, and high-speed bus and third by consolidating the design and debug environment into a single platform-based design system that affords the designer comp visibility and control.The C-SIDE software suite includes tools used to compile C and assemblage code for execution on the CS2112s embedded microprocessor, and Verilog simulation and synthesis tools used to create parallel datapath kernels which run on the CS2112s reconfigurable processing fabric. In addendum to code generation tools, the package chairs source-level debugging tools that support simulation and real-time debugging. Chameleons design approach leverages the methods employed by most of todays communications system designers.The designer starts with a C program that models signal processing functions of the baseband system. Having identified the dataflow intensive functional blocks, the designer implements them in the RCP to accelerate them by 10- to 100-fold. The designer creates tantamount(predicate) functions for those blocks, called kernels, in Chameleons reconfigurable assembly language-like design entry language. The assembler then mechanically generates standar d Verilog for these kernels that the designer can verify with commercial Verilog simulators.Using these tools, the designer can compare testbench results for the original C functions with similar results for the Verilog kernels. In the next phase, the designer synthesises the Verilog kernels using Chameleons synthesis tools targeting Chameleon technology. At the end, the tools output a bit file that is used to configure the RCP. The designer then integrates the application level C code with Verilog kernels and the rest of the standard C function. Chameleons C-SIDE compiling program and linker technology makes this integration step transparent to the designer.The CS2112 development environment makes all chip registers and memory locations accessible through a development solace that enables full processor-like debugging, including features like single-stepping and setting breakpoints. Before actually productising the system, the designer must often perform a system-level simulation of the data flow within the context of the overall system. Chameleons development board enables the designer to connect multiple RCPs to other devices in the system using the PCI bus and/or programmable I/O pins.This helps prove the design concept, and enables the designer to profile the performance of the self-coloured basestation system in a real-world environment. With telecommunications OEMs facing shrinking product animation cycles and increasing market pressures, not to mention the constant flux of protocols and standards, its more incumbent than ever to have a platform thats reconfigurable. This is where the chameleon chips are going to make its effect felt. The Chameleon CS2112 Package is a high-bandwidth, reconfigurable communications processor aimed at ? second- and third-generation wireless base stations fixed point wireless local loop (WLL) ? voice over IP ? DSL(digital reviewer line) ? High end dsp operations ? 2G-3G wireless base stations ? software defined radio ? security processing traditionalistic solutions such as FPGAs and DSPs lack the performance for high-bandwidth applications, and fixed function solutions like ASICs incur unimaginable limits Each product in the CS2000 family has the same fundamental functional blocks a 32-bit RISC processor, a full-featured memory dominance, a PCI controller, and a reconfigurable processing fabric, all of which are interconnected by a high-speed system bus.The preceding(prenominal) mentioned fabric comprises an array of reconfigurable tiles used to implement the desired algorithms. Each tile contains seven 32-bit reconfigurable datapath units, four blocks of local store memory, two 1624-bit multipliers, and a control logic unit. Basic Architecture pic Components ? 32-bit Risc ARC processor 125MHz ? 64 bit memory controller ? 32 bit PCI controller ? reconfigurable processing fabric (RPF) ? high speed system bus ? programmable I/O (160 pins) ? DMA Subsystem ? Configuration Subsystem More on the ar chitecture of RPF 4 Slices with 3 Tiles in each.Each tile can be reconfigured at runtime Tiles contain Datapath social units Local Store Memories 1624 multipliers Control Logic Unit The C-SIDE design system is a fully integrated tool suite, with C compiler, Verilog synthe sizer, full-chip simulator, as well as a debug and verification environment an element not readily found in ASIC and FPGA design flows, jibe to Chameleon. Still, reconfigurable chips represent an attempt to heighten the silk hat(p) features of hard-wired custom chips, which are fast and cheap, and programmable logic device (PLD) chips, which are flexible and easily brought to market.Unlike PLDs, mercurials reconfigurable chips can be reprogrammed every few nanoseconds, rewiring circuits so they are processing orbiculate positioning satellite signals one moment or CDMA cellular signals the next, have in mind of the chips as consisting of libraries with preset hardware designs and blackboards. Upon rece iving instructions from software, the chip takes a hardware component from the library (which is stored as software in memory) and puts it on the chalkboard (the chip). The chip wires itself instantly to run the software and dispatches it.The hardware can then be erased for the next cycle. With this style of computing, its chips can operate 80 generation as fast as a custom chip but still consume less power and board space, which translates into lower costs. The company believes that soft silicon, or chips that can be reconfigured on the fly, can be the heart of multifunction camcorders or digital television sets. With programmable logic devices, designers use bum software tools to quickly develop, simulate, and test their designs. Then, a design can be quickly programmed into a device, and immediately tested in a live circuit.The PLD that is used for this prototyping is the exact same PLD that will be used in the final outturn of a piece of end equipment, such as a network route r, a DSL modem, a DVD player, or an automotive navigation system. The two major types of programmable logic devices are field programmable gate arrays (FPGAs) and complex programmable logic devices (CPLDs). Of the two, FPGAs offer the highest amount of logic closeness, the most features, and the highest performance FPGAs are used in a wide variety of applications ranging from data processing and storage, to instrumentation, telecommunications, and digital signal processing.To overcome these limitations and offer a flexible, cost-effective solution, many new entrants to the DSP market are extolling the virtues of configurable and reconfigurable DSP designs. This latest melodic line of DSP architectures promises greater flexibility to quickly adapt to numerous and fast-changing standards. Plus, they claim to get hold of higher performance without adding silicon area, cost, design time, or power consumption. In essence, because the architecture isnt rigid, the reconfigurable DSP let s the developer tailor the hardware for a specific task, achieving the right size and cost for the target application.Moreover, the same platform can be reused for other applications. Because development tools are a critical part of this solutionin fact, theyre true enablersthe newcomers also ensure that the tools are robust and tightly linked to the devices flexible architectures. duration providing an intuitive, integrated development environment for the designers, the manufacturers ensure affordability as well. RECONFIGURING THE computer architecture Some of the new configurable DSP architectures are reconfigurable toothat is, developers can castrate their landscape on the fly, depending on the incoming data stream.This capability permits dynamic reconfigurability of the architecture as demanded by the application. Proponents of such chips are proclaiming an era of chip-on-demand, wherein new algorithms can be accommodated on-chip in real time via software. This eliminates the cumbersome job of fitting the latest algorithms and protocols into existing rigid hardware. A reconfigurable communications processor (RCP) can reconfigured for different processing algorithms in one clock cycle. Chameleon designers are revising the architecture to create a chip that can address a much broader range of applications.Plus, the supplier is preparing a new, more user-friendly suite of tools for traditional DSP designers. Thus, the company is dropping the term reconfigurability for the new architecture and going with a more traditional name, the streaming data processor (SDP). Though the SDP will include a reconfigurable processing fabric, it will be substantially altered, the company says. Unlike the older RCP, the new chip wont have the ARM RISC core, and it will support a much higher clock rate. Additionally, it will be implemented in a 0. 13-m CMOS process to meet the signal processing needs of a much broader market.Further details await the release of SDP sometime i n the first quarter of 2003. While Chameleon is in the redesign mode, QuickSilver Technologies is in the test mode. This reconfigurable proponent, which prefers to call its architecture an adaptive computing work or ACM, has realized its first silicon test chip. In fact, the tests luff that it outperforms a hardwired, fixed-function ASIC in processing compute-intensive cdma2000 algorithms, like system acquisition, rake finger, and set maintenance. For example, the ASICs nominal speed for searching 215 phase offsets in a basic multipath search algorithm is 3. seconds. The ACM test chip took just one second at a 25-MHz clock speed to perform the same number of searches in a cdma2000 handset. Likewise, the device accomplishes over 57,000 allowances per second in rake-finger operation to cycle through all operations in this application every 52 s (Fig. 1). In the set-maintenance application, the chip is almost three times faster than an ASIC, claims QuickSilver. THE power of a compu ter stems from the fact that its behaviour can be changed with little more than a dose of new software.A desktop PC efficiency, for example, be browsing the Internet one minute, and running a spreadsheet or entering the virtual world of a computer game the next. But the ability of a microprocessor (the chip that is at the heart of any PC) to handle such a variety of tasks is both a strength and a weaknessbecause hardware dedicated to a particular job can do things so much faster. Recognising this, the designers of modern PCs often hand over such tasks as processing 3-D graphics, decode and playing movies, and processing soundthings that could, in theory, be done by the basic microprocessorto specialist chips.These chips are designed to do their particular jobs exceedingly fast, but they are inflexible in comparison with a microprocessor, which does its best to be a jack-of-all-trades. So the hardware approach is faster, but using software is more flexible. At the moment, such rec onfigurable chips are used principally as a way of conjuring up specialist hardware in a hurry. Rather than designing and building an entirely new chip to carry out a particular function, a circuit designer can use an FPGA instead. This speeds up the design process enormously, because making changes becomes as simple as downloading a new configuration into the chip.Chameleon Systems also develops reconfigurable chips for the high-end telecom-switching market. RECONFIGURABLE PROCESSORS A reconfigurable processor is a microprocessor with erasable hardware that can rewire itself dynamically. This allows the chip to adapt effectively to the programming tasks demanded by the particular software they are interfacing with at any given time. Ideally, the reconfigurable processor can transform itself from a video chip to a central processing unit (cpu) to a graphics chip, for example, all optimized to allow applications to run at the highest possible speed.The new chips can be called a chip on demand. In practical terms, this ability can translate to immense flexibility in terms of device functions. For example, a single device could serve as both a camera and a tape recorder (among numerous other possibilities) you would simply download the desired software and the processor would reconfigure itself to optimize performance for that function. Reconfigurable processors, competing in the market with traditional hard-wired chips and several types of programmable microprocessors. Programmable chips have been in existence for over ten years.Digital signal processors (DSPs), for example, are high-performance programmable chips used in cell phones, automobiles, and various types of music players. While microprocessors have been the dominant devices in use for general-purpose computing for the last-place decade, there is still a large gap between the computational efficiency of microprocessors and custom silicon. Reconfigurable devices, such as FPGAs, have come approximate to closing that gap, offering a 10x benefit in computational parsimony over microprocessors, and often offering another potential 10x improvement in yielded functional density on low granularity operations.On highly regular computations, reconfigurable architectures have a clear superiority to traditional processor architectures. On tasks with high functional diversity, microprocessors use silicon more competently than reconfigurable devices. The BRASS project is developing a coupled architecture which allow a reconfigurable array and processor core to cooperate efficiently on computational tasks, exploiting the strengths of both architectures. We are developing an architecture and a effigy component that will combine a processor and a high performance reconfigurable array on a single chip.The reconfigurable array dilates the usefulness and efficiency of the processor by providing the means to tailor its circuits for special tasks. The processor improves the efficiency of the reconfigurable array for irregular, general-purpose computation. We anticipate that a processor combine with reconfigurable resources can achieve a significant performance improvement over either a separate processor or a separate reconfigurable device on an interesting range of problems drawn from embedded computing applications. As such, we hope to demonstrate that this composite device is an ideal system element for embedded processing.Reconfigurable devices have proven extremely efficient for veritable types of processing tasks. The key to their cost/performance advantage is that conventional processors are often limited by instruction bandwidth and execution restrictions or by an insufficient number or type of functional units. Reconfigurable logic exploits more program parallelism. By dedicating significantly less instruction memory per active computing element, reconfigurable devices achieve a 10x improvement in functional density over microprocessors.At the same time this lower memory ratio allows reconfigurable devices to deploy active capacity at a finer joted level, allowing them to realize a higher yield of their raw capacity, sometimes as much as 10x, than conventional processors. The high functional density characteristic of reconfigurable devices comes at the expense of the high functional diversity characteristic of microprocessors. Microprocessors have evolved to a highly optimized configuration with clear cost/performance advantages over reconfigurable arrays for a large set of tasks with high functional diversity.By combining a reconfigurable array with a processing core we hope to achieve the best of both worlds. While it is possible to combine a conventional processor with commercial reconfigurable devices at the circuit board level, integration radically changes the i/o costs and design point for both devices, resulting in a qualitatively different system. Notably, the lower on-chip communication costs allow efficient cooperation betwe en the processor and array at a finer grain than is sensible with discrete designs. RECONFIGURABLE COMPUTINGWhen we talk about reconfigurable computing were usually talking about FPGA-based system designs. Unfortunately, that doesnt qualify the term precisely tolerable. System designers use FPGAs in many different ways. The most common use of an FPGA is for prototyping the design of an ASIC. In this scenario, the FPGA is present only on the prototype hardware and is replaced by the corresponding ASIC in the final achievement system. This use of FPGAs has nothing to do with reconfigurable computing. However, many system designers are choosing to cede the FPGAs as part of the production hardware.Lower FPGA prices and higher gate counts have helped drive this change. Such systems retain the execution speed of dedicated hardware but also have a great deal of functional flexibility. The logic within the FPGA can be changed if or when it is necessary, which has many advantages. For exa mple, hardware bug fixes and upgrades can be administered as easily as their software counterseparate. In order to support a new version of a network protocol, you can redesign the internal logic of the FPGA and send the sweetening to the affected customers by email. erst theyve downloaded the new logic design to the system and restarted it, theyll be able to use the new version of the protocol. This is configurable computing reconfigurable computing goes one step further. Reconfigurable computing involves manipulation of the logic within the FPGA at run-time. In other words, the design of the hardware may change in response to the demands placed upon the system while it is running. Here, the FPGA acts as an execution engine for a variety of different hardware functions some executing in parallel, others in serial much as a CPU acts as an execution engine for a variety of software threads.We might even go so far as to call the FPGA a reconfigurable processing unit (RPU). Reconfi gurable computing allows system designers to execute more hardware than they have gates to fit, which works especially well when there are parts of the hardware that are occasionally idle. One theoretical application is a smart cellular phone that supports multiple communication and data protocols, though just one a time. When the phone passes from a geographic region that is served by one protocol into a region that is served by another, the hardware is mechanically reconfigured.This is reconfigurable computing at its best, and using this approach it is possible to design systems that do more, cost less, and have shorter design and implementation cycles. Reconfigurable computing has several advantages. ? First, it is possible to achieve greater functionality with a simpler hardware design. Because not all of the logic must be present in the FPGA at all times, the cost of supporting additional features is reduced to the cost of the memory indispensable to store the logic design. Co nsider again the multiprotocol cellular phone.It would be possible to support as many protocols as could be fit into the available on-board ROM. It is even conceivable that new protocols could be uploaded from a base station to the handheld phone on an as-needed basis, thus requiring no additional memory. ? The second advantage is lower system cost, which does not manifest itself exactly as you might expect. On a low-volume product, there will be some production cost savings, which result from the elimination of the expense of ASIC design and fabrication.However, for higher-volume products, the production cost of fixed hardware may actually be lower. We have to think in terms of lifetime system costs to see the savings. Systems based on reconfigurable computing are upgradable in the field. Such changes extend the useful life of the system, thus reducing lifetime costs. ? The final advantage of reconfigurable computing is reduced time-to-market. The fact that youre no longer using an ASIC is a big help in this respect. There are no chip design and prototyping cycles, which eliminates a large amount of development effort.In addition, the logic design remains flexible right up until (and even after) the product ships. This allows an incremental design flow, a luxury not typically available to hardware designers. You can even ship a product that meets the minimum requirements and add features after deployment. In the case of a networked product like a set-top box or cellular telephone, it may even be possible to make such enhancements without customer involvement. RECONFIGURABLE HARDWARE Traditional FPGAs are configurable, but not run-time reconfigurable.Many of the older FPGAs expect to read their configuration out of a serial EEPROM, one bit at a time. And they can only be made to do so by asserting a chip reset signal. This means that the FPGA must be reprogrammed in its entirety and that its previous internal state cannot be captured beforehand. Though these f eatures are compatible with configurable computing applications, they are not sufficient for reconfigurable computing. In order to benefit from run-time reconfiguration, it is necessary that the FPGAs involved have some or all of the following features.The more of these features they have, the more flexible can be the system design. Deciding which hardware objects to execute and when Swapping hardware objects into and out of the reconfigurable logic Performing routing between hardware objects or between hardware objects and the hardware object framework. Of course, having software manage the reconfigurable hardware usually means having an embedded processor or microcontroller on-board. (We expect several vendors to introduce single-chip solutions that combine a CPU core and a block of reconfigurable logic by years end. The embedded software that runs there is called the run-time environment and is equivalent to the operating system that manages the execution of multiple software th reads. Like threads, hardware objects may have priorities, deadlines, and contexts, etc. It is the job of the run-time environment to organize this information and make decisions based upon it. The reason we need a run-time environment at all is that there are decisions to be made while the system is running. And as human designers, we are not available to make these decisions. So we impart these responsibilities to a piece of software.This allows us to write our application software at a very high level of abstraction. To do this, the run-time environment must first locate space within the RPU that is large enough to execute the given hardware object. It must then perform the necessary routing between the hardware objects inputs and outputs and the blocks of memory reserved for each data stream. Next, it must stop the appropriate clock, reprogram the internal logic, and restart the RPU. Once the object starts to execute, the run-time environment must continuously monitor the hardwa re objects status flags to determine when it is done executing.Once it is done, the caller can be notified and given the results. The run-time environment is then free to reclaim the reconfigurable logic gates that were taken up by that hardware object and to wait for additional requests to arrive from the application software. The principal benefits of reconfigurable computing are the ability to execute larger hardware designs with fewer gates and to realize the flexibility of a software-based solution while retaining the execution speed of a more traditional, hardware-based approach. This makes doing more with less a reality.In our own business we have seen tremendous cost savings, simply because our systems do not become archaic as quickly as our competitors because reconfigurable computing enables the addition of new features in the field, allows rapid implementation of new standards and protocols on an as-needed basis, and protects their investment in computing hardware. Wheth er you do it for your customers or for yourselves, you should at least consider using reconfigurable computing in your next design. You may find, as we have, that the benefits far exceed the initial learning curve.And as reconfigurable computing becomes more popular, these benefits will only increase. ADVANTAGES OF RECONFIGURABILITY The term reconfigurable computing has come to refer to a loose class of embedded systems. Many system-on-a-chip (SoC) computer designs provide reconfigurability options that provide the high performance of hardware with the flexibility of software. To most designers, SoC means encapsulating one or more processing elementsthat is, general-purpose embedded processors and/or digital signal processor (DSP) cores on with memory, input/output devices, and other hardware into a single chip. These versatile chips can erform many different functions. However, while SoCs offer choices, the user can choose only among functions that already reside inside the device. Developers also create ASICschips that handle a limited set of tasks but do them very quickly. The limitation of most types of complex hardware devicesSoCs, ASICs, and general-purpose cpusis that the logical hardware functions cannot be modified once the silicon design is complete and fabricated. Consequently, developers are typically forced to amortize the cost of SoCs and ASICs over a product lifetime that may be extremely short in todays volatilisable technology environment.Solutions involving combinations of cpus and FPGAs allow hardware functionality to be reprogrammed, even in deployed systems, and enable medical instrument OEMs to develop new platforms for applications that require rapid adaptation to input. The technologies combined provide the best of both worlds for system-level design. Careful analysis of computational requirements reveals that many algorithms are well suited to high-speed sequential processing, many can benefit from parallel processing capabilities, an d many can be broken down into components that are split between the two.With this in mind, it makes wizard to always use the best technology for the job at hand. Processors are best suited to general-purpose processing and high-speed sequential processing (as are DSPs), while FPGAs excel at high-speed parallel processing. The general-purpose capability of the cpu enables it to perform system management very well, and allows it to be used to control the content of the FPGAs contained in the system.This symbiotic relationship between cpus and FPGAs also means that the FPGA can off-load computationally intensive algorithms from the cpu, allowing the processor to unload more time working on general-purpose tasks such as data analysis, and more time communicating with a printer or other equipment. Conclusion These new chips called chameleon chips are able to rewire themselves on the fly to create the exact hardware needed to run a piece of software at the utmost speed. an example of s uch kind of a chip is a chameleon chip. his can also be called a chip on demand Reconfigurable computing goes a step beyond programmable chips in the matter of flexibility. It is not only possible but relatively commonplace to rewrite the silicon so that it can perform new functions in a split second. Reconfigurable chips are simply the extreme end of programmability. Highly flexible processors that can be reconfigured remotely in the field, Chameleons chips are designed to simplify communication system design while delivering increased price/performance numbers.The chameleon chip is a high bandwidth reconfigurable communications processor (RCP). it aims at changing a systems design from a remote location. this will mean more versatile handhelds. Its applications are in, data-intensive Internet,DSP,wireless basestations, voice compression, software-defined radio, high-performance embedded telecom and datacom applications, xDSL concentrators,fixed wireless local loop, multichannel v oice compression, multiprotocol packet and cell processing protocols.Its advantages are that it can create customized communications signal processors ,it has increased performance and channel count, and it can more quickly adapt to new requirements and standards and it has lower development costs and reduce risk. A FUTURISTIC DREAM One day, someone will make a chip that does everything for the ultimate consumer device. The chip will be smart enough to be the brains of a cell phone that can transmit or receive calls anywhere in the world. If the reception is poor, the phone will automatically adjust so that the quality improves.At the same time, the device will also serve as a handheld organizer and a player for music, videos, or games. Unfortunately, that chip doesnt exist today. It would require flexibility high performance low power and low cost But we might be getting closer. Now a new kind of chip may reshape the semiconductor landscape. The chip adapts to any programming t ask by effectively erasing its hardware design and regenerating new hardware that is perfectly suited to run the software at hand.These chips, referred to as reconfigurable processors, could contention the balance of power that has preserved a decade-long standoff between programmable chips and hard-wired custom chips. These new chips are able to rewire themselves on the fly to create the exact hardware needed to run a piece of software at the utmost speed. an example of such kind of a chip is a chameleon chip. this can also be called a chip on demand Reconfigurable computing goes a step beyond programmable chips in the matter of flexibility.It is not only possible but relatively commonplace to rewrite the silicon so that it can perform new functions in a split second. Reconfigurable chips are simply the extreme end of programmability. If these pliable chips can reach a cost-performance parity with hard-wired chips, customers will chuck the smooth hard-wired solutions. And if si licon can indeed become dynamic, then so will the gadgets of the information age. No longer will you have to buy a camera and a tape recorder. You could just buy one gadget, and then download a new function for it when you want to take some pictures or make a recording.Just think of the possibilities for the fickle consumer. Programmable logic chips, which are arrays of memory cells that can be programmed to perform hardware functions using software tools, are more flexible than DSP chips but slower and more expensive For consumers, this means that the day isnt far away when a cell phone can be used to talk, transmit video images, connect to the Internet, maintain a calendar, and serve as entertainment during travel delays without the need to plug in adapter hardware REFERENCES BOOKS Wei Qin Presentation , Oct 2000 (The part of the presentation regarding CS2000 is covered in this page) IEEE conference on Tele-communication, 2001. WEBSITES www. chameleon systems. com www. thinkd igit. com www. ieee. org www. entecollege. com www. iec. org www. quicksilver technologies. com www. xilinx. com outline Chameleon chips are chips whose circuitry can be tailored specifically for the problem at hand. Chameleon chips would be an extension of what can already be done with field-programmable gate arrays (FPGAS). An FPGA is covered with a grid of wires.At each crossover, theres a switch that can be semipermanently opened or closed by sending it a special signal. Usually the chip must first be inserted in a little box that sends the programming signals. But now, labs in Europe, Japan, and the U. S. are developing techniques to rewire FPGA-like chips anytimeand even software that can map out circuitry thats optimized for specific problems. The chips still wont change colors. But they may well color the way we use computers in years to come. It is a fusion between custom integrated circuits and programmable logic. n the case when we are doing highly performance orien ted tasks custom chips that do one or two things spectacularly rather than lot of things averagely is used. Now using field programmed chips we have chips that can be rewired in an instant. Thus the benefits of customization can be brought to the mass market. CONTENTS ? INTRODUCTION ? CHAMELEON CHIPS ? ADVANTAGES AND APPLICATION ? FPGA ? CS2112 ? RECONFIGURING THE ARCHITECTURE ? RECONFIGURABLE PROCESSORS ? RECONFIGURABLE COMPUTING ? RECONFIGURABLE HARDWARE ? ADVANTAGES OF RECONFIGURABILITY ? CONCLUSION pic